1. Field of the Invention
The present invention relates to technology of manufacturing a semiconductor device for predicting film thickness of a thin film formed on the semiconductor device.
2. Description of the Related Art
Flatness is required in each layer as the semiconductor device becomes finer and multilayered. Specifically, in a wiring step of semiconductor device manufacturing, uniform planarization of a substrate surface applied with copper plating, etc., by polishing with a technology such as chemical mechanical planarization (CMP) has become important to improve the quality.
Polishing conditions are important to appropriately polish the copper plating formed on the substrate surface. The polishing conditions include, for example, polishing time, pressure of a polishing pad, and rotation speed when polishing, and the conditions need to be changed in accordance with film thickness of the copper plating.
Conventionally, using a test element group (TEG), optimal polishing conditions have been searched by conducting a film thickness predicting simulation of calculating the film thickness of the copper plating formed on the substrate surface with an equation model that expresses volume and height of the copper plating (for example, Japanese Patent Application Laid-Open Publication No. 2003-257915).
However, in some cases, deviation between the film thickness of the copper plating calculated by the film thickness predicting simulation and the actual film thickness of the copper plating formed on the substrate surface became large according to the conventional technology.
Therefore, a substrate surface could not be appropriately planarized in some cases, and connections of wirings or focus of wiring pattern do not match due to irregularity on the substrate surface, thereby causing a low yield.
The optimal polishing time may be searched by trial and error of a user. For example, a user polishes a substrate surface forming copper plating under certain polishing conditions and measures the film thickness of the copper plating after polishing. The user searches optimal polishing conditions to planarize the substrate surface by repeating the operation under various polishing conditions.
However, measurements of the film thickness need to be repeatedly conducted under various polishing conditions to search the optimal polishing conditions with this method. Therefore, tremendous operation time is required, thereby increasing designing periods and manufacturing costs.